
19
21454314fa
LTC2145-14/
LTC2144-14/LTC2143-14
TIMING DIAGRAMS
Double Data Rate LVDS Output Mode Timing
All Outputs Are Differential and Have LVDS Levels
tD
tC
tL
BIT 0
A-6
BIT 1
A-6
BIT 0
A-5
BIT 1
A-5
BIT 0
A-4
BIT 1
A-4
BIT 0
A-3
BIT 1
A-3
BIT 0
A-2
BIT 12
A-6
BIT 13
A-6
BIT 12
A-5
BIT 13
A-5
BIT 12
A-4
BIT 13
A-4
BIT 12
A-3
BIT 13
A-3
BIT 12
A-2
ENC–
ENC+
D1_0_1+
D1_12_13+
BIT 0
B-6
BIT 1
B-6
BIT 0
B-5
BIT 1
B-5
BIT 0
B-4
BIT 1
B-4
BIT 0
B-3
BIT 1
B-3
BIT 0
B-2
BIT 12
B-6
BIT 13
B-6
BIT 12
B-5
BIT 13
B-5
BIT 12
B-4
BIT 13
B-4
BIT 12
B-3
BIT 13
B-3
BIT 12
B-2
OF
B-6
OF
A-6
OF
B-5
OF
A-5
OF
B-4
OF
A-4
OF
B-3
OF
A-3
OF
B-2
D2_0_1+
D2_12_13+
CLKOUT+
CLKOUT–
OF2_1+
D1_0_1–
D1_12_13–
D2_0_1–
D2_12_13–
OF2_1–
21454314 TD03
tH
tAP
A + 1
A + 2
A + 4
A + 3
A
CH 1
ANALOG
INPUT
tAP
B + 1
B + 2
B + 4
B + 3
B
CH 2
ANALOG
INPUT
A6
tS
tDS
A5
A4
A3
A2
A1
A0
XX
D7
D6
D5
D4
D3
D2
D1
D0
XX
CS
SCK
SDI
R/W
SDO
HIGH IMPEDANCE
SPI Port Timing (Readback Mode)
SPI Port Timing (Write Mode)
tDH
tDO
tSCK
tH
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
21454314 TD04
CS
SCK
SDI
R/W
SDO
HIGH IMPEDANCE